# 1 "FWlib/apt32f102_gpt.c"
# 1 "E:\\APT_Landscape_mode\\APT32F1023_New\\Source//"
# 1 "<built-in>"
# 1 "<command-line>"
# 1 "FWlib/apt32f102_gpt.c"
# 19 "FWlib/apt32f102_gpt.c"
# 1 "include/apt32f102_gpt.h" 1
# 23 "include/apt32f102_gpt.h"
# 1 "include/apt32f102.h" 1
# 23 "include/apt32f102.h"
# 1 "include/apt32f102_types_local.h" 1
# 63 "include/apt32f102_types_local.h"
typedef signed char S8_T;
typedef short S16_T;
typedef long S32_T;


typedef unsigned char U8_T;
typedef unsigned short U16_T;
typedef unsigned long U32_T;
typedef unsigned long long U64_T;


typedef float F32_T;
typedef double F64_T;


typedef U8_T B_T;
# 100 "include/apt32f102_types_local.h"
typedef enum {ENABLE = 1, DISABLE = !ENABLE} ClockStatus, FunctionalStatus;
typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;




typedef volatile U32_T CSP_REGISTER_T;
typedef volatile U16_T CSP_REGISTER16_T;
typedef volatile U8_T CSP_REGISTER8_T;




typedef unsigned char UINT8;
typedef signed char SINT8;


typedef unsigned short UINT16;
typedef signed short SINT16;


typedef unsigned long UINT32;
typedef signed long SINT32;

typedef void VOID;
typedef signed char CHAR;
typedef unsigned char BOOL;
typedef signed long TIME_T;

typedef float SINGLE;



typedef double DOUBLE;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
} REG8;

typedef struct
{
  unsigned bit0 : 1;
  unsigned bit1 : 1;
  unsigned bit2 : 1;
  unsigned bit3 : 1;
  unsigned bit4 : 1;
  unsigned bit5 : 1;
  unsigned bit6 : 1;
  unsigned bit7 : 1;
  unsigned bit8 : 1;
  unsigned bit9 : 1;
  unsigned bit10: 1;
  unsigned bit11: 1;
  unsigned bit12: 1;
  unsigned bit13: 1;
  unsigned bit14: 1;
  unsigned bit15: 1;
} REG16;






typedef char STRING_3[4];
typedef char STRING_5[6];
typedef char STRING_8[9];
typedef char STRING_10[11];
typedef char STRING_12[13];
typedef char STRING_16[17];
typedef char STRING_24[25];
typedef char STRING_30[31];
typedef char STRING_32[33];
typedef char STRING_48[49];
typedef char STRING_50[51];
typedef char STRING_60[61];
typedef char STRING_80[81];
typedef char STRING_132[133];
typedef char STRING_256[257];
typedef char STRING_512[513];
# 24 "include/apt32f102.h" 2
# 1 "include/apt32f102_ck801.h" 1
# 85 "include/apt32f102_ck801.h"
typedef enum IRQn
{

        ISR_Restart = -32,
        ISR_Misaligned_Access = -31,
        ISR_Access_Error = -30,
        ISR_Divided_By_Zero = -29,
        ISR_Illegal = -28,
        ISR_Privlege_Violation = -27,
        ISR_Trace_Exection = -26,
        ISR_Breakpoint_Exception = -25,
        ISR_Unrecoverable_Error = -24,
        ISR_Idly4_Error = -23,
        ISR_Auto_INT = -22,
        ISR_Auto_FINT = -21,
        ISR_Reserved_HAI = -20,
        ISR_Reserved_FP = -19,
        ISR_TLB_Ins_Empty = -18,
        ISR_TLB_Data_Empty = -17,

        INTC_CORETIM_IRQn = 0,
        INTC_TIME1_IRQn = 1,
        INTC_UART0_IRQn = 2,
        INTC_GPIOA2_IRQn = 8,
} IRQn_Type;


void INTC_Init(void);
void force_interrupt(IRQn_Type IRQn);

void CK_CPU_EnAllNormalIrq(void);
void CK_CPU_DisAllNormalIrq(void);
# 25 "include/apt32f102.h" 2




typedef struct {
 volatile unsigned int ReservedA[4];
 volatile unsigned int CORET_CSR;
 volatile unsigned int CORET_RVR;
 volatile unsigned int CORET_CVR;
 volatile unsigned int CORET_CALIB;
 volatile unsigned int ReservedB[56];
 volatile unsigned int ISER;
 volatile unsigned int ReservedC[15];
 volatile unsigned int IWER;
 volatile unsigned int ReservedD[15];
 volatile unsigned int ICER;
 volatile unsigned int ReservedE[15];
 volatile unsigned int IWDR;
 volatile unsigned int ReservedF[15];
 volatile unsigned int ISPR;
 volatile unsigned int ReservedG[31];
 volatile unsigned int ICPR;
 volatile unsigned int ReservedH[31];
 volatile unsigned int IABR;
 volatile unsigned int ReservedI[63];
 volatile unsigned int IPR[8];
 volatile unsigned int ReservedJ[504];
 volatile unsigned int ISR;
 volatile unsigned int IPTR;
} CSP_CK801_T;



typedef volatile struct {
 volatile unsigned int IDR ;
 volatile unsigned int CEDR ;
 volatile unsigned int SRR ;
 volatile unsigned int CMR ;
 volatile unsigned int CR ;
 volatile unsigned int MR ;
 volatile unsigned int FM_ADDR ;
 volatile unsigned int Reserved ;
 volatile unsigned int KR ;
 volatile unsigned int IMCR ;
 volatile unsigned int RISR ;
 volatile unsigned int MISR ;
 volatile unsigned int ICR ;
} CSP_IFC_T ;



typedef volatile struct {
 volatile unsigned int IDCCR;
 volatile unsigned int GCER;
 volatile unsigned int GCDR;
 volatile unsigned int GCSR;
 volatile unsigned int CKST;
 volatile unsigned int RAMCHK;
 volatile unsigned int EFLCHK;
 volatile unsigned int SCLKCR;
 volatile unsigned int PCLKCR;
 volatile unsigned int _RSVD0;
 volatile unsigned int PCER0;
 volatile unsigned int PCDR0;
 volatile unsigned int PCSR0;
 volatile unsigned int PCER1;
 volatile unsigned int PCDR1;
 volatile unsigned int PCSR1;
 volatile unsigned int OSTR;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int LVDCR;
 volatile unsigned int CLCR;
 volatile unsigned int PWRCR;
 volatile unsigned int PWRKEY;
 volatile unsigned int _RSVD3;
 volatile unsigned int _RSVD4;
 volatile unsigned int OPT1;
 volatile unsigned int OPT0;
 volatile unsigned int WKCR;
 volatile unsigned int _RSVD5;
 volatile unsigned int IMER;
 volatile unsigned int IMDR;
 volatile unsigned int IMCR;
 volatile unsigned int IAR;
 volatile unsigned int ICR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int RSR;
 volatile unsigned int EXIRT;
 volatile unsigned int EXIFT;
 volatile unsigned int EXIER;
 volatile unsigned int EXIDR;
 volatile unsigned int EXIMR;
 volatile unsigned int EXIAR;
 volatile unsigned int EXICR;
 volatile unsigned int EXIRS;
 volatile unsigned int IWDCR;
 volatile unsigned int IWDCNT;
 volatile unsigned int IWDEDR;
 volatile unsigned int IOMAP0;
 volatile unsigned int IOMAP1;
 volatile unsigned int CINF0;
 volatile unsigned int CINF1;
 volatile unsigned int FINF0;
 volatile unsigned int FINF1;
 volatile unsigned int FINF2;
 volatile unsigned int _RSVD6;
 volatile unsigned int ERRINF;
 volatile unsigned int UID0 ;
 volatile unsigned int UID1 ;
 volatile unsigned int UID2 ;
 volatile unsigned int PWROPT;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVSWF;
 volatile unsigned int UREG0;
 volatile unsigned int UREG1;
 volatile unsigned int UREG2;
 volatile unsigned int UREG3;
} CSP_SYSCON_T;



 typedef volatile struct
 {
    volatile unsigned int EN;
    volatile unsigned int SWTRG;
    volatile unsigned int CH0CON0;
    volatile unsigned int CH0CON1;
    volatile unsigned int CH1CON0;
    volatile unsigned int CH1CON1;
    volatile unsigned int CH2CON0;
    volatile unsigned int CH2CON1;
 volatile unsigned int _RSVD0;
 volatile unsigned int _RSVD1;
 volatile unsigned int _RSVD2;
 volatile unsigned int _RSVD3;
    volatile unsigned int CH3CON;
 volatile unsigned int CH4CON;
 volatile unsigned int CH5CON;
 volatile unsigned int CH6CON;
 volatile unsigned int CH7CON;
 } CSP_ETCB_T, *CSP_ETCB_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CCR;
   volatile unsigned int TCH_CON0;
   volatile unsigned int TCH_CON1;
   volatile unsigned int TCH_SCCR;
   volatile unsigned int TCH_SENPRD;
   volatile unsigned int TCH_VALBUF;
   volatile unsigned int TCH_SENCNT;
   volatile unsigned int TCH_TCHCNT;
   volatile unsigned int TCH_THR;
   volatile unsigned int Reserved0;
   volatile unsigned int TCH_RISR;
   volatile unsigned int TCH_IER;
   volatile unsigned int TCH_ICR;
   volatile unsigned int TCH_RWSR;
   volatile unsigned int TCH_OVW_THR;
   volatile unsigned int TCH_OVF;
   volatile unsigned int TCH_OVT;
   volatile unsigned int TCH_SYNCR;
   volatile unsigned int TCH_EVTRG;
   volatile unsigned int TCH_EVPS;
   volatile unsigned int TCH_EVSWF;
} CSP_TKEY_T, *CSP_TKEY_PTR;



typedef volatile struct
{
   volatile unsigned int TCH_CHVAL[18];
   volatile unsigned int TCH_SEQCON[18];
} CSP_TKEYBUF_T, *CSP_TKEYBUF_PTR;



 typedef volatile struct
 {
    volatile unsigned int ECR;
    volatile unsigned int DCR;
    volatile unsigned int PMSR;
    volatile unsigned int Reserved0;
    volatile unsigned int CR;
    volatile unsigned int MR;
    volatile unsigned int SHR;
    volatile unsigned int CSR;
    volatile unsigned int SR;
    volatile unsigned int IER;
    volatile unsigned int IDR;
    volatile unsigned int IMR;
    volatile unsigned int SEQ[16];
    volatile unsigned int PRI;
    volatile unsigned int TDL0;
    volatile unsigned int TDL1;
    volatile unsigned int SYNCR;
    volatile unsigned int Reserved1;
    volatile unsigned int Reserved2;
    volatile unsigned int EVTRG;
    volatile unsigned int EVPS;
    volatile unsigned int EVSWF;
    volatile unsigned int ReservedD[27];
    volatile unsigned int DR[16];
    volatile unsigned int CMP0;
    volatile unsigned int CMP1;
 volatile unsigned int DRMASK;
 } CSP_ADC12_T, *CSP_ADC12_PTR;



 typedef volatile struct
 {
    volatile unsigned int CONLR;
    volatile unsigned int CONHR;
    volatile unsigned int WODR;
    volatile unsigned int SODR;
    volatile unsigned int CODR;
    volatile unsigned int ODSR;
    volatile unsigned int PSDR;
    volatile unsigned int FLTEN;
    volatile unsigned int PUDR;
    volatile unsigned int DSCR;
    volatile unsigned int OMCR;
    volatile unsigned int IECR;
 volatile unsigned int IEER;
 volatile unsigned int IEDR;
 } CSP_GPIO_T, *CSP_GPIO_PTR;

 typedef volatile struct
 {
 volatile unsigned int IGRPL;
    volatile unsigned int IGRPH;
 volatile unsigned int IGREX;
    volatile unsigned int IO_CLKEN;
 } CSP_IGRP_T, *CSP_IGRP_PTR;



 typedef volatile struct
 {
    volatile unsigned int DATA;
    volatile unsigned int SR;
    volatile unsigned int CTRL;
    volatile unsigned int ISR;
    volatile unsigned int BRDIV;
    volatile unsigned int ReservedA[20];
 } CSP_UART_T, *CSP_UART_PTR;



typedef struct
{
 volatile unsigned int CR0;
 volatile unsigned int CR1;
 volatile unsigned int DR;
 volatile unsigned int SR;
 volatile unsigned int CPSR;
 volatile unsigned int IMSCR;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int ICR;
} CSP_SSP_T, *CSP_SSP_PTR;



typedef struct
{
 volatile unsigned int CR;
 volatile unsigned int TXCR0;
 volatile unsigned int TXCR1;
 volatile unsigned int TXBUF;
 volatile unsigned int RXCR0;
 volatile unsigned int RXCR1;
 volatile unsigned int RXCR2;
 volatile unsigned int RXBUF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
} CSP_SIO_T, *CSP_SIO_PTR;



 typedef volatile struct
 {
    unsigned int CR;
    unsigned int TADDR;
    unsigned int SADDR;
    unsigned int ReservedD;
    unsigned int DATA_CMD;
    unsigned int SS_SCLH;
    unsigned int SS_SCLL;
    unsigned int FS_SCLH;
    unsigned int FS_SCLL;
    unsigned int ReservedA;
    unsigned int ReservedC;
    unsigned int RX_FLSEL;
    unsigned int TX_FLSEL;
    unsigned int RX_FL;
    unsigned int TX_FL;
    unsigned int ENABLE;
    unsigned int STATUS;
    unsigned int ReservedB;
    unsigned int SDA_TSETUP;
    unsigned int SDA_THOLD;
    unsigned int SPKLEN;

    unsigned int ReservedE;
 unsigned int MISR;
    unsigned int IMSCR;
    unsigned int RISR;
    unsigned int ICR;
    unsigned int ReservedF;
    unsigned int SCL_TOUT;
    unsigned int SDA_TOUT;
    unsigned int TX_ABRT;
    unsigned int GCALL;
    unsigned int NACK;
 } CSP_I2C_T, *CSP_I2C_PTR;



 typedef struct
 {
    volatile unsigned int CADATAH;
    volatile unsigned int CADATAL;
    volatile unsigned int CACON;
    volatile unsigned int INTMASK;
 } CSP_CA_T, *CSP_CA_PTR;



 typedef struct
 {
 volatile unsigned int CEDR;
 volatile unsigned int RSSR;
 volatile unsigned int PSCR;
 volatile unsigned int CR;
 volatile unsigned int SYNCR;
 volatile unsigned int GLDCR;
 volatile unsigned int GLDCFG;
 volatile unsigned int GLDCR2;
 volatile unsigned int Reserved0;
 volatile unsigned int PRDR;
 volatile unsigned int Reserved1;
 volatile unsigned int CMPA;
 volatile unsigned int CMPB;
 volatile unsigned int Reserved2;
 volatile unsigned int Reserved3;
 volatile unsigned int CMPLDR;
 volatile unsigned int CNT;
 volatile unsigned int AQLDR;
 volatile unsigned int AQCRA;
 volatile unsigned int AQCRB;
 volatile unsigned int Reserved4;
 volatile unsigned int Reserved5;
 volatile unsigned int Reserved6;
 volatile unsigned int AQOSF;
 volatile unsigned int AQCSF;
 volatile unsigned int Reserved7;
 volatile unsigned int Reserved8;
 volatile unsigned int Reserved9;
 volatile unsigned int Reserved10;
 volatile unsigned int Reserved11;
 volatile unsigned int Reserved12;
 volatile unsigned int Reserved13;
 volatile unsigned int Reserved14;
 volatile unsigned int Reserved15;
 volatile unsigned int Reserved16;
 volatile unsigned int Reserved17;
 volatile unsigned int Reserved18;
 volatile unsigned int Reserved19;
 volatile unsigned int Reserved20;
 volatile unsigned int Reserved21;
 volatile unsigned int Reserved22;
 volatile unsigned int Reserved23;
 volatile unsigned int Reserved24;
 volatile unsigned int Reserved25;
 volatile unsigned int Reserved26;
 volatile unsigned int Reserved27;
 volatile unsigned int TRGFTCR;
 volatile unsigned int TRGFTWR;
 volatile unsigned int EVTRG;
 volatile unsigned int EVPS;
 volatile unsigned int EVCNTINIT;
 volatile unsigned int EVSWF;
 volatile unsigned int RISR;
 volatile unsigned int MISR;
 volatile unsigned int IMCR;
 volatile unsigned int ICR;
 volatile unsigned int REGLINK;

 }CSP_GPT_T,*CSP_GPT_PTR;



 typedef struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int GLDCR;
   volatile unsigned int GLDCFG;
   volatile unsigned int GLDCR2;
   volatile unsigned int HRCFG;
   volatile unsigned int PRDR;
   volatile unsigned int PHSR;
   volatile unsigned int CMPA;
   volatile unsigned int CMPB;
   volatile unsigned int CMPC;
   volatile unsigned int CMPD;
   volatile unsigned int CMPLDR;
   volatile unsigned int CNT;
   volatile unsigned int AQLDR;
   volatile unsigned int AQCRA;
   volatile unsigned int AQCRB;
   volatile unsigned int AQCRC;
   volatile unsigned int AQCRD;
   volatile unsigned int AQTSCR;
   volatile unsigned int AQOSF;
   volatile unsigned int AQCSF;
   volatile unsigned int DBLDR;
   volatile unsigned int DBCR;
   volatile unsigned int DPSCR;
   volatile unsigned int DBDTR;
   volatile unsigned int DBDTF;
   volatile unsigned int CPCR;
   volatile unsigned int EMSRC;
   volatile unsigned int EMSRC2;
   volatile unsigned int EMPOL;
   volatile unsigned int EMECR;
   volatile unsigned int EMOSR;
   volatile unsigned int Reserved;
   volatile unsigned int EMSLSR;
   volatile unsigned int EMSLCLR;
   volatile unsigned int EMHLSR;
   volatile unsigned int EMHLCLR;
   volatile unsigned int EMFRCR;
   volatile unsigned int EMRISR;
   volatile unsigned int EMMISR;
   volatile unsigned int EMIMCR;
   volatile unsigned int EMICR;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINIT;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
   volatile unsigned int REGLINK;
   volatile unsigned int REGLINK2;
   volatile unsigned int REGPROT;
} CSP_EPT_T, *CSP_EPT_PTR;



 typedef volatile struct
 {
   volatile unsigned int CEDR;
   volatile unsigned int RSSR;
   volatile unsigned int PSCR;
   volatile unsigned int CR;
   volatile unsigned int SYNCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int TRGFTCR;
   volatile unsigned int TRGFTWR;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int MISR;
   volatile unsigned int IMCR;
   volatile unsigned int ICR;
} CSP_LPT_T, *CSP_LPT_PTR;



 typedef struct
 {
   volatile unsigned int RSSR;
   volatile unsigned int CR;
   volatile unsigned int PSCR;
   volatile unsigned int PRDR;
   volatile unsigned int CMP;
   volatile unsigned int CNT;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVCNTINTI;
   volatile unsigned int EVSWF;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
} CSP_BT_T, *CSP_BT_PTR;



typedef struct
{
   volatile unsigned int IDR;
   volatile unsigned int CEDR;
   volatile unsigned int SRR;
   volatile unsigned int CR;
   volatile unsigned int SEED;
   volatile unsigned int DATAIN;
   volatile unsigned int DATAOUT;

} CSP_CRC_T, *CSP_CRC_PTR;



 typedef struct
 {
   volatile unsigned int TIMR;
   volatile unsigned int DATR;
   volatile unsigned int CR;
   volatile unsigned int CCR;
   volatile unsigned int ALRAR;
   volatile unsigned int ALRBR;
   volatile unsigned int SSR;
   volatile unsigned int CAL;
   volatile unsigned int RISR;
   volatile unsigned int IMCR;
   volatile unsigned int MISR;
   volatile unsigned int ICR;
   volatile unsigned int KEY;
   volatile unsigned int EVTRG;
   volatile unsigned int EVPS;
   volatile unsigned int EVSWF;
} CSP_RTC_T, *CSP_RTC_PTR;




 typedef struct
 {
  volatile unsigned int CR;
  volatile unsigned int CFGR;
  volatile unsigned int RISR;
  volatile unsigned int MISR;
  volatile unsigned int IMCR;
  volatile unsigned int ICR;
 }CSP_WWDT_T,*CSP_WWDT_PTR;



 typedef struct
 {
  volatile S32_T DIVIDENT;
  volatile S32_T DIVISOR;
  volatile S32_T QUOTIENT;
  volatile S32_T REMAIN;
  volatile unsigned int CR;
 }CSP_HWD_T,*CSP_HWD_PTR;
# 691 "include/apt32f102.h"
extern CSP_CK801_T *CK801 ;

extern CSP_IFC_T *IFC ;
extern CSP_SYSCON_T *SYSCON ;
extern CSP_ETCB_T *ETCB ;

extern CSP_TKEY_T *TKEY ;
extern CSP_TKEYBUF_T *TKEYBUF ;
extern CSP_ADC12_T *ADC0 ;

extern CSP_GPIO_T *GPIOA0 ;
extern CSP_GPIO_T *GPIOB0 ;
extern CSP_IGRP_T *GPIOGRP ;

extern CSP_UART_T *UART0 ;
extern CSP_UART_T *UART1 ;
extern CSP_UART_T *UART2 ;
extern CSP_SSP_T *SPI0 ;
extern CSP_SIO_T *SIO0 ;
extern CSP_I2C_T *I2C0 ;
extern CSP_CA_T *CA0 ;

extern CSP_GPT_T *GPT0 ;

extern CSP_EPT_T *EPT0 ;

extern CSP_LPT_T *LPT ;
extern CSP_HWD_T *HWD ;
extern CSP_WWDT_T *WWDT ;
extern CSP_BT_T *BT0 ;
extern CSP_BT_T *BT1 ;

extern CSP_CRC_T *CRC ;
extern CSP_RTC_T *RTC ;


void MisalignedHandler(void) __attribute__((isr));
void IllegalInstrHandler(void) __attribute__((isr));
void AccessErrHandler(void) __attribute__((isr));
void BreakPointHandler(void) __attribute__((isr));
void UnrecExecpHandler(void) __attribute__((isr));
void Trap0Handler(void) __attribute__((isr));
void Trap1Handler(void) __attribute__((isr));
void Trap2Handler(void) __attribute__((isr));
void Trap3Handler(void) __attribute__((isr));
void PendTrapHandler(void) __attribute__((isr));

void CORETHandler(void) __attribute__((isr));
void SYSCONIntHandler(void) __attribute__((isr));
void IFCIntHandler(void) __attribute__((isr));
void ADCIntHandler(void) __attribute__((isr));
void EPT0IntHandler(void) __attribute__((isr));
void WWDTHandler(void) __attribute__((isr));
void EXI0IntHandler(void) __attribute__((isr));
void EXI1IntHandler(void) __attribute__((isr));
void EXI2to3IntHandler(void) __attribute__((isr));
void EXI4to9IntHandler(void) __attribute__((isr));
void EXI10to15IntHandler(void) __attribute__((isr));
void UART0IntHandler(void) __attribute__((isr));
void UART1IntHandler(void) __attribute__((isr));
void UART2IntHandler(void) __attribute__((isr));
void I2CIntHandler(void) __attribute__((isr));
void GPT0IntHandler(void) __attribute__((isr));
void LEDIntHandler(void) __attribute__((isr));
void TKEYIntHandler(void) __attribute__((isr));
void SPI0IntHandler(void) __attribute__((isr));
void SIO0IntHandler(void) __attribute__((isr));
void CNTAIntHandler(void) __attribute__((isr));
void RTCIntHandler(void) __attribute__((isr));
void LPTIntHandler(void) __attribute__((isr));
void BT0IntHandler(void) __attribute__((isr));
void BT1IntHandler(void) __attribute__((isr));

extern int __divsi3 (int a, int b);
extern unsigned int __udivsi3 (unsigned int a, unsigned int b);
extern int __modsi3 (int a, int b);
extern unsigned int __umodsi3 (unsigned int a, unsigned int b);
extern void delay_nms(unsigned int t);
extern void delay_nus(unsigned int t);
# 24 "include/apt32f102_gpt.h" 2
# 33 "include/apt32f102_gpt.h"
typedef enum
{
    GPTCLK_DIS = 0,
 GPTCLK_EN = 1,
}GPT_CLK_TypeDef;



typedef enum
{
    GPT_PCLK = (0<<2),
 GPT_TRGUSR3 = (1<<2),
}GPT_CSS_TypeDef;



typedef enum
{
    GPT_SHADOW = (0<<6),
 GPT_IMMEDIATE= (1<<6),
}GPT_SHDWSTP_TypeDef;



typedef enum
{
    DIR_INCREASE = (0<<3),
 DIR_DECREASE= (1<<3),
}GPT_CNTDIR_TypeDef;



typedef enum
{
    GPT_INCREASE = (0<<0),
 GPT_DECREASE= (1<<0),
 GPT_IN_DECREASE= (2<<0),
}GPT_CNTMD_TypeDef;



typedef enum
{
    GPT_SWSYNDIS= (0<<2),
 GPT_SWSYNEN= (1<<2),
}GPT_SWSYN_TypeDef;



typedef enum
{
    GPT_IDLE_Z= (0<<3),
 GPT_IDLE_LOW= (1<<3),
}GPT_IDLEST_TypeDef;



typedef enum
{
 GPT_PRDLD_PEND= (0<<4),
 GPT_PRDLD_LOAD_SYNC= (1<<4),
 GPT_PRDLD_ZERO_LOAD_SYNC= (2<<4),
 GPT_PRDLD_IMMEDIATELY= (3<<4),
}GPT_PRDLD0_TypeDef;



typedef enum
{
    GPT_CAP_DIS= (0<<8),
 GPT_CAP_EN= (1<<8),
}GPT_CAPLDEN_TypeDef;



typedef enum
{
    GPT_BURST_DIS= (0<<9),
 GPT_BURST_EN= (1<<9),
}GPT_BURST_TypeDef;



typedef enum
{
    GPT_CG_CHAX= (0<<11),
 GPT_CG_CHBX= (1<<11),
}GPT_CGSRC_TypeDef;



typedef enum
{
    GPT_CGFLT_00= (0<<13),
 GPT_CGFLT_02= (1<<13),
 GPT_CGFLT_03= (2<<13),
 GPT_CGFLT_04= (3<<13),
 GPT_CGFLT_06= (4<<13),
 GPT_CGFLT_08= (5<<13),
 GPT_CGFLT_16= (6<<13),
 GPT_CGFLT_32= (7<<13),
}GPT_CGFLT_TypeDef;



typedef enum
{
 GPT_PRDLD_ZERO= (0<<16),
 GPT_PRDLD_PRD= (1<<16),
 GPT_PRDLD_ZERO_PRD= (2<<16),
 GPT_PRDLD_NONE= (3<<16),
}GPT_PSCLD_TypeDef;



typedef enum
{
 GPT_CAPMD_CONTINUOUS= (0<<20),
 GPT_CAPMD_ONCE= (1<<20),
}GPT_CAPMD_TypeDef;



typedef enum
{
 GPT_LDARST_EN= (0<<23),
 GPT_LDARST_DIS= (1<<23),
}GPT_LDARST_TypeDef;



typedef enum
{
 GPT_LDBRST_EN= (0<<23),
 GPT_LDBRST_DIS= (1<<23),
}GPT_LDBRST_TypeDef;



typedef enum
{
 GPT_OPM_CONTINUOUS= (0<<6),
 GPT_OPM_ONCE= (1<<6),
}GPT_OPM_TypeDef;



typedef enum
{
 GPT_CKS_PCLK= (0<<10),
 GPT_CKS_PCLKDIV2= (1<<10),
}GPT_CKS_TypeDef;



typedef enum
{
 GPT_CAPTURE_MODE= (0<<18),
 GPT_WAVE_MODE= (1<<18),
}GPT_WAVE_TypeDef;



typedef enum
{
 GPT_SYNCUSR0_EN= (1<<0),
 GPT_SYNCUSR1_EN= (1<<0),
 GPT_SYNCUSR2_EN= (1<<0),
 GPT_SYNCUSR3_EN= (1<<0),
 GPT_SYNCUSR4_EN= (1<<0),
 GPT_SYNCUSR5_EN= (1<<0)
}GPT_SYNCENX_TypeDef;




typedef enum
{
 GPT_OST_CONTINUOUS= (0<<8),
 GPT_OST_ONCE= (1<<8),
}GPT_OSTMDX_TypeDef;



typedef enum
{
 GPT_TXREARM_DIS= (0<<22),
 GPT_TXREARM_T1= (1<<22),
 GPT_TXREARM_T2= (2<<22),
 GPT_TXREARM_T1_T2= (3<<22),
}GPT_TXREARM0_TypeDef;




typedef enum
{
 GPT_TRGO0SEL_SR0= (0<<24),
 GPT_TRGO0SEL_SR1= (1<<24),
 GPT_TRGO0SEL_SR2= (2<<24),
 GPT_TRGO0SEL_SR3= (3<<24),
 GPT_TRGO0SEL_SR4= (4<<24),
 GPT_TRGO0SEL_SR5= (5<<24),
 GPT_TRGO0SEL_RSVD= (6<<24),
}GPT_TRGO0SEL_TypeDef;




typedef enum
{
 GPT_TRG10SEL_SR0= (0<<27),
 GPT_TRG10SEL_SR1= (1<<27),
 GPT_TRG10SEL_SR2= (2<<27),
 GPT_TRG10SEL_SR3= (3<<27),
 GPT_TRG10SEL_SR4= (4<<27),
 GPT_TRG10SEL_SR5= (5<<27),
 GPT_TRG10SEL_RSVD= (6<<27),
}GPT_TRGO1SEL_TypeDef;



typedef enum
{
 GPT_AREARM_DIS= (0<<30),
 GPT_AREARM_ZERO= (1<<30),
 GPT_AREARM_PRD= (2<<30),
 GPT_AREARM_ZERO_PRD= (3<<30),
}GPT_AREARM_TypeDef;



typedef enum
{
 GPT_TRGEV0 = (0x01 << 0),
 GPT_TRGEV1 = (0x01 << 1),
 GPT_TRGEV2 = (0x01 << 2),
 GPT_TRGEV3 = (0x01 << 3),
}GPT_IMSCR_TypeDef;



typedef enum
{
 GPT_CHA_PB01 = 0,
 GPT_CHA_PA09 = 1,
 GPT_CHA_PA010 = 2,
 GPT_CHB_PA010 = 3,
 GPT_CHB_PA011 = 4,
 GPT_CHB_PB00 = 5,
 GPT_CHB_PB01 = 6,
}GPT_IOSET_TypeDef;



typedef enum
{
 GPT_CMPA_SHADOW = (0x00 << 0),
 GPT_CMPA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWCMPA_TypeDef;



typedef enum
{
 GPT_CMPB_SHADOW = (0x00 << 1),
 GPT_CMPB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWCMPB_TypeDef;



typedef enum
{
 GPT_LoadA_ZERO = (0x01 << 4),
 GPT_LoadA_PRD = (0x02 << 4),
 GPT_LoadA_EXT_SYNC = (0x04 << 4),
 GPT_LoadA_NONE = (0x00 << 4),
}GPT_LDAMD_TypeDef;



typedef enum
{
 GPT_LoadB_ZERO = (0x01 << 4),
 GPT_LoadB_PRD = (0x02 << 4),
 GPT_LoadB_EXT_SYNC = (0x04 << 4),
 GPT_LoadB_NONE = (0x00 << 4),
}GPT_LDBMD_TypeDef;




typedef enum
{
 GPT_WAVEA_SHADOW = (0x00 << 0),
 GPT_WAVEA_IMMEDIATE = (0x01 << 0),
}GPT_SHDWAQA_TypeDef;



typedef enum
{
 GPT_WAVEB_SHADOW = (0x00 << 1),
 GPT_WAVEB_IMMEDIATE = (0x01 << 1),
}GPT_SHDWAQB_TypeDef;



typedef enum
{
 GPT_AQLDA_ZERO = (0x01 << 2),
 GPT_AQLDA_PRD = (0x02 << 2),
 GPT_AQLDA_EXT_SYNC = (0x04 << 2),
 GPT_AQLDA_NONE = (0x00 << 2),
}GPT_AQLDA_TypeDef;



typedef enum
{
 GPT_AQLDB_ZERO = (0x01 << 5),
 GPT_AQLDB_PRD = (0x02 << 5),
 GPT_AQLDB_EXT_SYNC = (0x04 << 5),
 GPT_AQLDB_NONE = (0x00 << 5),
}GPT_AQLDB_TypeDef;



typedef enum
{
 GPT_CASEL_CMPA = (0x00 << 20),
 GPT_CASEL_CMPB = (0x01 << 20),
}GPT_CASEL_TypeDef;



typedef enum
{
 GPT_CBSEL_CMPA = (0x00 << 22),
 GPT_CBSEL_CMPB = (0x01 << 22),
}GPT_CBSEL_TypeDef;



typedef enum
{
 GPT_CHA = 0,
 GPT_CHB = 1,
}GPT_GPTCHX_TypeDef;



typedef enum
{
 GPT_CHA_FORCE_DIS = 0,
 GPT_CHA_FORCE_EN = 1,
}GPT_CHAFORCE_TypeDef;



typedef enum
{
 GPT_CHB_FORCE_DIS = 0<<4,
 GPT_CHB_FORCE_EN = 1<<4,
}GPT_CHBFORCE_TypeDef;



typedef enum
{
 GPT_FORCELD_ZERO = (0<<16),
 GPT_FORCELD_PRD = (1<<16),
 GPT_FORCELD__ZERO_PRD = (3<<16),
}GPT_FORCELD_TypeDef;



typedef enum
{
 GPT_FORCECHA_LOW = (1<<0),
 GPT_FORCECHA_HIGH = (2<<0),
}GPT_FORCEA_TypeDef;



typedef enum
{
 GPT_FORCECHB_LOW = (1<<2),
 GPT_FORCECHB_HIGH = (2<<2),
}GPT_FORCEB_TypeDef;



typedef enum
{
    GPT_SRCSEL_DIS= (0<<0),
 GPT_SRCSEL_TRGUSR0EN= (1<<0),
 GPT_SRCSEL_TRGUSR1EN= (2<<0),
 GPT_SRCSEL_TRGUSR2EN= (3<<0),
 GPT_SRCSEL_TRGUSR3EN= (4<<0),
 GPT_SRCSEL_TRGUSR4EN= (5<<0),
 GPT_SRCSEL_TRGUSR5EN= (6<<0)
}GPT_SRCSEL_TypeDef;



typedef enum
{
    GPT_BLKINV_DIS= (0<<4),
 GPT_BLKINV_EN= (1<<4),
}GPT_BLKINV_TypeDef;



typedef enum
{
    GPT_ALIGNMD_PRD= (0<<5),
 GPT_ALIGNMD_ZRO= (1<<5),
 GPT_ALIGNMD_PRD_ZRO= (2<<5),
 GPT_ALIGNMD_T1= (3<<5),
}GPT_ALIGNMD_TypeDef;



typedef enum
{
    GPT_CROSSMD_DIS= (0<<7),
 GPT_CROSSMD_EN= (1<<7),
}GPT_CROSSMD_TypeDef;



typedef enum
{
    GPT_TRGSRC0_DIS= (0<<0),
 GPT_TRGSRC0_ZRO= (1<<0),
 GPT_TRGSRC0_PRD= (2<<0),
 GPT_TRGSRC0_ZRO_PRD= (3<<0),
 GPT_TRGSRC0_CMPA_INC= (4<<0),
 GPT_TRGSRC0_CMPA_DEC= (5<<0),
 GPT_TRGSRC0_CMPB_INC= (6<<0),
 GPT_TRGSRC0_CMPB_DEC= (7<<0),
 GPT_TRGSRC0_EXTSYNC= (0X0C<<0),
 GPT_TRGSRC0_PE0= (0X0D<<0),
 GPT_TRGSRC0_PE1= (0X0E<<0),
 GPT_TRGSRC0_PE2= (0X0F<<0),
}GPT_TRGSRC0_TypeDef;



typedef enum
{
    GPT_TRGSRC1_DIS= (0<<4),
 GPT_TRGSRC1_ZRO= (1<<4),
 GPT_TRGSRC1_PRD= (2<<4),
 GPT_TRGSRC1_ZRO_PRD= (3<<4),
 GPT_TRGSRC1_CMPA_INC= (4<<4),
 GPT_TRGSRC1_CMPA_DEC= (5<<4),
 GPT_TRGSRC1_CMPB_INC= (6<<4),
 GPT_TRGSRC1_CMPB_DEC= (7<<4),
 GPT_TRGSRC1_EXTSYNC= (0X0C<<4),
 GPT_TRGSRC1_PE0= (0X0D<<4),
 GPT_TRGSRC1_PE1= (0X0E<<4),
 GPT_TRGSRC1_PE2= (0X0F<<4),
}GPT_TRGSRC1_TypeDef;




typedef enum
{
    GPT_CNT0INIT_DIS= (0<<16),
 GPT_CNT0INIT_EN= (1<<16),
}GPT_CNT0INIT_TypeDef;




typedef enum
{
    GPT_CNT1INIT_DIS= (0<<17),
 GPT_CNT1INIT_EN= (1<<17),
}GPT_CNT1INIT_TypeDef;




typedef enum
{
    GPT_ESYN0OE_DIS= (0<<20),
 GPT_ESYN0OE_EN= (1<<20),
}GPT_ESYN0OE_TypeDef;




typedef enum
{
    GPT_ESYN1OE_DIS= (0<<21),
 GPT_ESYN1OE_EN= (1<<21),
}GPT_ESYN1OE_TypeDef;





typedef enum
{
 GPT_CNTMD_increase = ((CSP_REGISTER_T)(0x00ul << 0)),
 GPT_CNTMD_decrease = ((CSP_REGISTER_T)(0x01ul << 0)),
 GPT_CNTMD_increaseTOdecrease = ((CSP_REGISTER_T)(0x02ul << 0))
}GPT_CNTMD_SELECTE_Type;




typedef enum
{
 GPT_CAPMD_Once = ((CSP_REGISTER_T)(0x01ul << 20)),
 GPT_CAPMD_Continue = ((CSP_REGISTER_T)(0x00ul << 20))
}GPT_CAPMD_SELECTE_Type;




typedef enum
{
 GPT_LDCRST_EN = ((CSP_REGISTER_T)(0x00ul << 25)),
 GPT_LDCRST_DIS = ((CSP_REGISTER_T)(0x01ul << 25))
}GPT_LOAD_CMPC_RST_CMD_Type;



typedef enum
{
 GPT_LDDRST_EN = ((CSP_REGISTER_T)(0x00ul << 26)),
 GPT_LDDRST_DIS = ((CSP_REGISTER_T)(0x01ul << 26))
}GPT_LOAD_CMPD_RST_CMD_Type;
# 646 "include/apt32f102_gpt.h"
extern void GPT_DeInit(void);
extern void GPT_IO_Init(GPT_IOSET_TypeDef IONAME);
extern void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX);
extern void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
      GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX);
extern void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX);
extern void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
      U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX);
extern void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX);
extern void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX);
extern void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX);
extern void GPT_Debug_Mode(FunctionalStatus NewState);
extern void GPT_Start(void);
extern void GPT_Stop(void);
extern void GPT_Soft_Reset(void);
extern void GPT_Cap_Rearm(void);
extern void GPT_REARM_Write(void);
extern U8_T GPT_REARM_Read(void);
extern void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA);
extern U16_T GPT_PRDR_Read(void);
extern U16_T GPT_CMPA_Read(void);
extern U16_T GPT_CMPB_Read(void);
extern U16_T GPT_CNT_Read(void);
extern void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X);
extern void GPT_INT_ENABLE(void);
extern void GPT_INT_DISABLE(void);
extern void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
       GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx);
extern void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
      U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA);
extern void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
      GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt);
extern void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
     , GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
     GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP );
# 20 "FWlib/apt32f102_gpt.c" 2







void GPT_DeInit(void)
{
 GPT0->CEDR = 0xBE980000;
 GPT0->RSSR = (0x00000000);
 GPT0->PSCR = (0x00000000);
 GPT0->CR = 0X00010010;
 GPT0->SYNCR = (0x00000000);
 GPT0->GLDCR = (0x00000000);
 GPT0->GLDCFG = (0x00000000);
 GPT0->GLDCR2 = (0x00000000);
 GPT0->PRDR = (0x00000000);
 GPT0->CMPA = (0x00000000);
 GPT0->CMPB = (0x00000000);
 GPT0->CMPLDR = 0X00002490;
 GPT0->CNT = (0x00000000);
 GPT0->AQLDR = 0X00000024;
 GPT0->AQCRA = (0x00000000);
 GPT0->AQCRB = (0x00000000);
 GPT0->AQOSF = 0X00000100;
 GPT0->AQCSF = (0x00000000);
 GPT0->TRGFTCR = (0x00000000);
 GPT0->TRGFTWR = (0x00000000);
 GPT0->EVTRG = (0x00000000);
 GPT0->EVPS = (0x00000000);
 GPT0->EVCNTINIT = (0x00000000);
 GPT0->EVSWF = (0x00000000);
 GPT0->RISR = (0x00000000);
 GPT0->MISR = (0x00000000);
 GPT0->IMCR = (0x00000000);
 GPT0->ICR = (0x00000000);
 GPT0->REGLINK = (0x00000000);
}





void GPT_IO_Init(GPT_IOSET_TypeDef IONAME)
{
 if(IONAME==GPT_CHA_PB01)
 {
  GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000050;
 }
 if(IONAME==GPT_CHA_PA09)
 {
  GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFFF0F)|0x00000050;
 }
 if(IONAME==GPT_CHA_PA010)
 {
  GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000600;
 }
 if(IONAME==GPT_CHB_PA010)
 {
  GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFFF0FF)|0x00000700;
 }
 if(IONAME==GPT_CHB_PA011)
 {
  GPIOA0->CONHR=(GPIOA0->CONHR & 0XFFFF0FFF)|0x00006000;
 }
 if(IONAME==GPT_CHB_PB00)
 {
  GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFFF0)|0x00000004;
 }
 if(IONAME==GPT_CHB_PB01)
 {
  GPIOB0->CONLR=(GPIOB0->CONLR & 0XFFFFFF0F)|0x00000060;
 }
}






void GPT_Configure(GPT_CLK_TypeDef GPTCLKX,GPT_CSS_TypeDef GCSSX,GPT_SHDWSTP_TypeDef GSHDWSTPX,U16_T GPSCX)
{
 GPT0->CEDR = GPTCLKX| GCSSX|GSHDWSTPX;
 GPT0->PSCR=GPSCX;
}







void GPT_WaveCtrl_Configure(GPT_CNTMD_TypeDef GCNTMDX,GPT_SWSYN_TypeDef GSWSYNX,GPT_IDLEST_TypeDef GIDLEX,GPT_PRDLD0_TypeDef GPRDLD0,GPT_OPM_TypeDef GOPMX,
      GPT_BURST_TypeDef GBURSTX,GPT_CKS_TypeDef GCKS,GPT_CGSRC_TypeDef CGSRCX,GPT_CGFLT_TypeDef CGFLT,GPT_PSCLD_TypeDef PSCLDX)
{
 GPT0->CR =GCNTMDX|GSWSYNX|GIDLEX|GPRDLD0|GOPMX|GBURSTX|GCKS|CGSRCX|CGFLT|PSCLDX|GPT_WAVE_MODE;
}






void GPT_WaveLoad_Configure(GPT_SHDWAQA_TypeDef SHDWAQAX,GPT_SHDWAQB_TypeDef SHDWAQBX,GPT_AQLDA_TypeDef AQLDAX, GPT_AQLDB_TypeDef AQLDBX)
{
 GPT0->AQLDR=SHDWAQAX|SHDWAQBX|AQLDAX|AQLDBX;
}





void GPT_WaveOut_Configure(GPT_GPTCHX_TypeDef GPTCHX,GPT_CASEL_TypeDef CASELX,GPT_CBSEL_TypeDef CBSELX,U8_T ZROX,U8_T PRDX,U8_T CAUX,
      U8_T CADX,U8_T CBUX,U8_T CBDX,U8_T T1UX,U8_T T1DX,U8_T T2UX,U8_T T2DX)
{
 if(GPTCHX==GPT_CHA)
 {
 GPT0->AQCRA=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18);
 }
 if(GPTCHX==GPT_CHB)
 {
 GPT0->AQCRB=CASELX|CBSELX|(ZROX<<0)|(PRDX<<2)|(CAUX<<4)|(CADX<<6)|(CBUX<<8)|(CBDX<<10)|(T1UX<<12)|(T1DX<<14)|(T2UX<<16)|(T2DX<<18);
 }
}
# 156 "FWlib/apt32f102_gpt.c"
void GPT_Capture_Config(GPT_CNTMD_SELECTE_Type GPT_CNTMD_SELECTE_X , GPT_CAPMD_SELECTE_Type GPT_CAPMD_SELECTE_X , GPT_CAPLDEN_TypeDef CAP_CMD
     , GPT_LDARST_TypeDef GPT_LOAD_CMPA_RST_CMD , GPT_LDBRST_TypeDef GPT_LOAD_CMPB_RST_CMD ,
     GPT_LOAD_CMPC_RST_CMD_Type GPT_LOAD_CMPC_RST_CMD , GPT_LOAD_CMPD_RST_CMD_Type GPT_LOAD_CMPD_RST_CMD, U8_T GPT_STOP_WRAP )
{
 GPT0->CR=(GPT0->CR&0xf800fec0)|GPT_CNTMD_SELECTE_X|(0x0<<2)|(0x0<<3)|(0x0<<4)|CAP_CMD|GPT_CAPMD_SELECTE_X|(0X0<<16)|(0x0<<18)|(GPT_STOP_WRAP<<21)|
    GPT_LOAD_CMPA_RST_CMD|GPT_LOAD_CMPB_RST_CMD|GPT_LOAD_CMPC_RST_CMD|GPT_LOAD_CMPD_RST_CMD;
}





void GPT_SyncSet_Configure(GPT_SYNCENX_TypeDef SYNCENx,GPT_OSTMDX_TypeDef OSTMDx,GPT_TXREARM0_TypeDef TXREARM0x,GPT_TRGO0SEL_TypeDef TRGO0SELx,
       GPT_TRGO1SEL_TypeDef TRGO1SELx,GPT_AREARM_TypeDef AREARMx)
{
 GPT0->SYNCR |= SYNCENx| OSTMDx| TXREARM0x |TRGO0SELx|TRGO1SELx|AREARMx;
}





void GPT_Trigger_Configure(GPT_SRCSEL_TypeDef SRCSELx,GPT_BLKINV_TypeDef BLKINVx,GPT_ALIGNMD_TypeDef ALIGNMDx,GPT_CROSSMD_TypeDef CROSSMDx,
      U16_T G_OFFSET_DATA,U16_T G_WINDOW_DATA)
{
 GPT0->TRGFTCR |= SRCSELx| BLKINVx|ALIGNMDx| CROSSMDx;
 GPT0->TRGFTWR |= G_OFFSET_DATA |(G_WINDOW_DATA<<16);

}





void GPT_EVTRG_Configure(GPT_TRGSRC0_TypeDef TRGSRC0x,GPT_TRGSRC1_TypeDef TRGSRC1x,GPT_ESYN0OE_TypeDef ESYN0OEx,GPT_ESYN1OE_TypeDef ESYN1OEx,
      GPT_CNT0INIT_TypeDef CNT0INITx,GPT_CNT1INIT_TypeDef CNT1INITx,U8_T TRGEV0prd,U8_T TRGEV1prd,U8_T TRGEV0cnt,U8_T TRGEV1cnt)
{
 GPT0->EVTRG |= TRGSRC0x |TRGSRC1x|ESYN0OEx|ESYN1OEx|CNT0INITx|CNT1INITx;
 GPT0->EVPS |= TRGEV0prd|(TRGEV1prd<<4)|(TRGEV0cnt<<16)|(TRGEV1cnt<<20);
}





void GPT_OneceForce_Out(GPT_CHAFORCE_TypeDef CHAFORCEX,U8_T AFORCE_STATUS,GPT_CHBFORCE_TypeDef CHBFORCEX,U8_T BFORCE_STATUS,GPT_FORCELD_TypeDef FORCELDX)
{
 GPT0->AQOSF =CHAFORCEX|CHBFORCEX|FORCELDX|(AFORCE_STATUS<<1)|(BFORCE_STATUS<<5);
}





void GPT_Force_Out(GPT_FORCEA_TypeDef FORCEAX,GPT_FORCEB_TypeDef FORCEBX)
{
 GPT0->AQCSF =FORCEAX|FORCEBX;
}





void GPT_CmpLoad_Configure(GPT_SHDWCMPA_TypeDef SHDWCMPAX,GPT_SHDWCMPB_TypeDef SHDWCMPBX,GPT_LDAMD_TypeDef LDAMDX,GPT_LDBMD_TypeDef LDBMDX)
{
 GPT0->CMPLDR=SHDWCMPAX|SHDWCMPBX|LDAMDX|LDBMDX;
}





void GPT_Debug_Mode(FunctionalStatus NewState)
{
 if (NewState != DISABLE)
 {
  GPT0->CEDR |= (0x01<<1);
 }
 else
 {
  GPT0->CEDR &= ~(0x01<<1);
 }
}





void GPT_Start(void)
{
 GPT0->RSSR |= 0X01;
}





void GPT_Stop(void)
{
 GPT0->RSSR &= 0XFFFFFFFE;
}





void GPT_Soft_Reset(void)
{
 GPT0->RSSR |= (0X5<<12);
}





void GPT_Cap_Rearm(void)
{
 GPT0->CR |= (0X01<<19);
}





void GPT_Mode_CMD(GPT_WAVE_TypeDef WAVEX)
{
 GPT0->CR |= WAVEX;
}





void GPT_REARM_Write(void)
{
 GPT0->SYNCR |= (0X1<<16);
}





U8_T GPT_REARM_Read(void)
{
 unsigned char value = 0;
    unsigned int dat = 0;
    dat=(GPT0->SYNCR)&(1<<16);
    if (dat)
 {
     value = 1;
 }
    return value;
}





void GPT_Period_CMP_Write(U16_T PRDR_DATA,U16_T CMPA_DATA,U16_T CMPB_DATA)
{
 GPT0->PRDR =PRDR_DATA;
 GPT0->CMPA =CMPA_DATA;
 GPT0->CMPB =CMPB_DATA;
}





U16_T GPT_PRDR_Read(void)
{
    return GPT0->PRDR;
}
U16_T GPT_CMPA_Read(void)
{
    return GPT0->CMPA;
}
U16_T GPT_CMPB_Read(void)
{
    return GPT0->CMPB;
}
U16_T GPT_CNT_Read(void)
{
    return GPT0->CNT;
}






void GPT_ConfigInterrupt_CMD(FunctionalStatus NewState,U32_T GPT_IMSCR_X)
{
 if (NewState != DISABLE)
 {
  GPT0->IMCR |= GPT_IMSCR_X;
 }
 else
 {
  GPT0->IMCR &= ~GPT_IMSCR_X;
 }
}






void GPT_INT_ENABLE(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x100 ) = (0x01ul<<9);
}





void GPT_INT_DISABLE(void)
{
 *(volatile UINT32 *) (0xE000E000 +0x180 ) = (0x01ul<<9);
}
